This invention relates to a built-in self-test (BIST) circuit. More specifically, the present invention relates to a BIST technique and circuitry for analog to digital converters (ADCs).
Testing mixed signal integrated circuits is known to be a difficult and time-consuming task. The problem is aggravated by the recent trend of integrating mixed-signal cores into a large digital environment to achieve system-on-a-chip integration. Mixing such circuits leads to ad-hoc and non-standard production test strategies which may require complex and expensive mixed-signal automatic test equipment (ATE).
Recent efforts address the question of mixed-signal test bus standardization which has led to the IEEE.1149.4 standard proposal. The IEEE.1149.4 standard may alleviate controllability and observability problems but cannot solve the problems related to test time and ATE requirements for testing modern high-speed and high-resolution mixed-signal circuits. A mixed-signal BIST approach may reduce test time and cost and allow testing of a mixed-signal ASIC on a digital ATE eliminating the need for expensive mixed-signal ATE.
Many methods for the on-chip testing of ADCs have been presented in the literature. The majority of existing techniques employ an on-chip DAC to apply analog stimuli to the ADC under test. Three problems have to be considered for these techniques. First, they may be limited to applications where one may find an ADC-DAC pair on the same chip. Second, the DAC used to test the ADC should have at least 2-bits of resolution more than the ADC under test. The third problem is fault masking in which a fault in DAC may compensate another fault in ADC. Thus, a need still exists to be able to test embedded ADC individually without using another data converter.
Other techniques which rely on the availability of a micro-controller or DSP core on-chip to test the ADC under test may not be applicable where such an on-chip resource are not available. Another technique, called the oscillation-test method, may be applied to test an ADC in which some small additional circuits are added in the feedback loop and the whole system is oscillated. Differential non-linearity (DNL) error and conversion speed may then be tested by measuring the oscillation frequency of the circuit under test. Test accuracy may be affected by extra components and the test requires precision frequency measurement which may require a long test-time and high testing costs.
Accordingly, the present invention provides a method and apparatus for on-chip testing of ADCs. The technique disclosed in the present invention is based on the delta-sigma modulator concept. A modulator loop may be constructed using the ADC under test, a digital comparator, a one-bit digital to analog converter (DAC), and an integrator. The analog input of the modulator input may be chosen to be zero. A digital comparator may then be used to inject the equivalent of an offset voltage into the loop using the digital input, DIN. A delta-sigma modulator attempts to cancel out the introduced offset voltage and shifts the ADC""s average input voltage to the analog voltage level equivalent to the DIN.
The whole system may be seen as a DAC converting the digital input, DIN, to its equivalent analog voltage, VOUT. If the digital input is switched from a code CB to a code CA, the analog output changes to VA from VB which are transition voltages associated with code CA and code CB consequently. The number of clock cycles (Clk) which the analog outputs takes to reach VA from VB may determine the distance between these two transition voltages. Therefore, the distance between each two predetermined transition voltages may be measured as a function of the number of clock cycles (CLK). If the two transition voltages are adjacent, differential non-linearity (DNL) may be measured. If the first transition voltage is zero, integral non-linearity (INL) may be measured at the upper transition voltage.
The BIST circuitry may also include a control logic which directs the whole operation. The control logic may be used to load Register A and Register B with proper values and determine which register is selected by the multiplexer. The control logic may also be used to count the number of clock cycles to determine DNL or INL for each predetermined code.